This invention relates generally to computer memory, and more particularly to providing on-die termination of a control signal bus.
Contemporary high performance computing main memory systems are generally composed of one or more memory devices, which are connected to one or more processors via one or more memory control elements. These memory devices are generally located on a memory card module and connected through a module connector to a mother board.
Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the main memory devices(s), and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc. Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power and cooling).
Current memory modules have terminators for control signals (e.g., command and address signals) on the memory module. Typically, the control signal bus is implemented in a fly-by routing with an external terminator located on the memory module after the last memory device. This takes up space on the memory module and adds to the cost of the memory module. On-die termination (ODT) is difficult to implement for a control signal bus because setting the ODT to on/off and to particular resistance values needs to be performed by executing some commands, and executing these commands requires that proper termination for control signals is already in place. Conventional methods to solve this problem include running the memory device at a very slow frequency during ODT setting and then raising the memory device to the normal frequency. Another solution includes adding an additional serial interface pin (e.g., an ODT signal pin) on each memory device. Both of these solutions require additional overhead and longer initialization time. In addition, neither solution allows different memory devices on a memory module to be programmed differently because the control signal bus is common to all of the memory devices on the memory module.